(a) Fields of the Invention
The present invention relates to semiconductor devices which have MIS transistors capable of accomplishing a further miniaturization and operable at high speed and with low power consumption, and to methods for fabricating such a device.
(b) Description of Related Art
Accompanied with high integration of semiconductor integrated circuits, miniaturization of MIS transistors in the circuits is demanded. To accomplish this miniaturization, MIS transistors are required which have a heavily-doped source and drain structure with shallow junctions of source and drain regions (see, for example, Japanese Unexamined Patent Publication No. H11-261069).
Hereinafter, an example of conventional methods for fabricating a semiconductor device with a MIS transistor will be described with reference to the accompanying drawings:
FIGS. 12A to 12E show sectional structures of a conventional semiconductor device in the order of its fabrication process steps.
First, in the step shown in FIG. 12A, boron (B) ions serving as a p-type impurity are implanted into a semiconductor substrate 101 made of p-type silicon on an implantation condition of an implantation energy of 10 keV and a dose of 2×1012 ions/cm2. Thereafter, thermal treatment is performed to form a p-type diffused channel layer 102 in a channel formation region of the semiconductor substrate 101.
Next, in the step shown in FIG. 12B, a gate oxide film 103 is formed on the semiconductor substrate 101 and subsequently a gate electrode 104 of polysilicon is formed on the gate oxide film 103.
Then, in the step shown in FIG. 12C, using the gate electrode 104 as a mask, arsenic (As) ions serving as an n-type impurity are implanted into the semiconductor substrate 101 to form n-type implanted extension layers 105A. Subsequently, using the gate electrode 104 as a mask, boron (B) ions serving as a p-type impurity are implanted into the semiconductor substrate 101 to form p-type implanted pocket layers 106A.
In the step shown in FIG. 12D, an insulating film is deposited over the semiconductor substrate 101, and then the deposited insulating film is subjected to an anisotropic etching to form sidewalls 107 on side surfaces of the gate electrode 104.
Next, in the step shown in FIG. 12E, using the gate electrode 104 and the sidewalls 107 as a mask, arsenic ions serving as an n-type impurity are implanted into the semiconductor substrate 101. Thereafter, the semiconductor substrate 101 is subjected to thermal treatment to form n-type diffused source and drain layers 108 in regions of the semiconductor substrate 101 located below respective sides of the sidewalls 107. In this treatment, n-type diffused extension layers 105 made by diffusion of the n-type implanted extension layers 105A are formed in regions of the semiconductor substrate 101 located below the sidewalls 107 and between the n-type diffused source and drain layers 108 and the p-type diffused channel layer 102, respectively, and p-type diffused pocket layers 106 made by diffusion of the p-type implanted pocket layer 106A are formed in regions of the semiconductor substrate 101 located below the n-type diffused extension layers 105, respectively.
In order to miniaturize the MIS transistor without manifesting a short channel effect, the conventional fabrication methods as described above tend to lower the implantation energy of the impurity ion for forming the n-type diffused extension layers 105 and increase the temperature of the thermal treatment for activation.